Andhra Loyola Institute of Engineering and Technology (ALIET), Vijayawada
Dear PrimeMOS team,
“We sincerely appreciate PrimeMOS Research & Solutions for its valuable contribution as the Technical Resource Organization for the Two-Day Workshop on 'Fundamentals of VLSI: RTL-to-GDSII Flow Using EDA Tools', organized by the Department of Electronics and Communication Engineering, in association with the ElectroCratz Club, at Andhra Loyola Institute of Engineering and Technology (Autonomous), Vijayawada, on 5th and 6th October 2026.”
“The workshop provided students with valuable exposure to the fundamentals of VLSI design and the RTL-to-GDSII flow using EDA tools, covering important concepts related to digital VLSI design, CMOS technology, RTL design, synthesis, physical design, and chip implementation.”
“The technical sessions, practical demonstrations, and hands-on guidance provided during the workshop helped the participants gain a better understanding of the practical aspects of VLSI design and the overall semiconductor design flow.”
“The efforts of PrimeMOS Research & Solutions, in collaboration with the Department of ECE and ElectroCratz Club, in promoting practical and concept-oriented learning in VLSI and EDA tools are sincerely appreciated.”
“We express our gratitude for your valuable contribution and technical support towards the successful conduct of the workshop. We wish PrimeMOS Research & Solutions continued success in its endeavors in the fields of VLSI, semiconductor design, research, and technical education.”
Fundamentals of VLSI: RTL to GDSII Using EDA Tools — Feedback Analytics
Team Performance Scorecard (16 Teams)
Overall Mean Rating: 4.62 / 5.00 • 4 Teams Scored Perfect 5.0/5.0| Team # | Students | Day 1 Avg | Day 2 Avg | Team Rating | Delivered RTL to GDSII Project | Rating Badge |
|---|---|---|---|---|---|---|
| Team 01 | 3 students | 5.00 / 5 | 4.67 / 5 | 4.83 / 5 | AND gate design & MUX 32x1 design | |
| Team 02 | 3 students | 4.67 / 5 | 4.67 / 5 | 4.67 / 5 | 8x3 Encoder, OR gate & AND gate | |
| Team 03 | 3 students | 4.33 / 5 | 4.00 / 5 | 4.17 / 5 | T Flip-Flop, Logic Gates, KLayout & Ubuntu | |
| Team 04 | 3 students | 4.33 / 5 | 4.67 / 5 | 4.50 / 5 | RTL to GDS Flow & Logic Gates Automation | |
| Team 05 | 3 students | 4.00 / 5 | 4.00 / 5 | 4.00 / 5 | 3-to-8 Decoder, AND Gate & OR Gate | |
| Team 06 ★ TOP | 2 students | 5.00 / 5 | 5.00 / 5 | 5.00 / 5 | 4-bit Down Counter & Physical Design Flow | |
| Team 07 | 3 students | 5.00 / 5 | 4.00 / 5 | 4.50 / 5 | SR Flip-Flop Layout & Ubuntu | |
| Team 08 | 3 students | 4.00 / 5 | 4.00 / 5 | 4.00 / 5 | Analog IC Flow, EDA Tools & CTS | |
| Team 09 | 3 students | 4.67 / 5 | 4.33 / 5 | 4.50 / 5 | Full Adder, AND & OR Gates, KLayout | |
| Team 10 | 2 students | 5.00 / 5 | 4.00 / 5 | 4.50 / 5 | D Flip-Flop, AND & NAND, OR Gates | |
| Team 11 | 3 students | 4.67 / 5 | 5.00 / 5 | 4.83 / 5 | Physical Design Flow & Circuit Implementation | |
| Team 12 ★ TOP | 3 students | 5.00 / 5 | 5.00 / 5 | 5.00 / 5 | MUX 1011, OpenLane & KLayout | |
| Team 13 ★ TOP | 3 students | 5.00 / 5 | 5.00 / 5 | 5.00 / 5 | Full Subtractor, OpenLane & VLSI Roadmap | |
| Team 14 | 3 students | 4.67 / 5 | 5.00 / 5 | 4.83 / 5 | 4-bit Up Counter & Logic Gates | |
| Team 15 | 3 students | 4.33 / 5 | 5.00 / 5 | 4.67 / 5 | AND, OR & XNOR Gate Level Designs | |
| Team 16 ★ TOP | 3 students | 5.00 / 5 | 5.00 / 5 | 5.00 / 5 | 4-bit ALU (Arithmetic Logic Unit in Linux/EDA) |
“Project of 4-bit down counter and got output — Excellent! The full RTL-to-GDSII flow covering synthesis, floorplanning, CTS, routing, physical verification and GDSII generation was executed with remarkable clarity.”
Challa Niveditha Reddy & Mandagiri Bhavya 23HP1A0483 23HP1A0469
“Software implementation of our 4-bit ALU project was excellent. The hands-on training using Linux EDA toolchains, TCL scripting, and understanding real-time digital cell placement made this workshop stand out.”
B. Ravindra, S. Seetaram & G. Yaswanth Yadav 24HP5A0406 23HP1A04B8
“Setting up WSL, Ubuntu, OpenLane, and KLayout on Day 1 laid the perfect groundwork. Implementing the MUX 1011 project and basic logic gates with zero errors on Day 2 was an excellent learning milestone.”
D. Adinarayana, K. Sai Chaitanya & N. Abhinash 24HP1A0496 24HP1A0453
“Very good explanation of the flow of topics from RTL to GDSII. Designed the 32x1 MUX and AND gate project successfully. The sessions gave us a clear route map for VLSI physical design careers.”
S. Mamatha & A. Guru Ashwani 24HP1A0409 24HP1A0406
“RTL to GDSII flow, installation of WSL, Ubuntu, and OpenLane were completed smoothly. Implemented the full subtractor project and gained invaluable insights from the comprehensive VLSI career roadmap.”
N. Yaswanth Reddy & N. Udaykiran 24HP1A04C8 25HP5A0411
“Learned hands-on design of circuits and physical design flow. Implemented RTL to GDS flow on basic logic gates and completed the 4-bit up counter project with excellent guidance.”
Sk. M. Sahil & P. Jayram 24HP1A04B4 24HP1A04?0
Geethanjali College of Engineering & Technology (GCET), Keesara
“On behalf of IETE GCET and the Department of Electronics & Communication Engineering, Geethanjali College of Engineering and Technology, Keesara, we extend our sincere appreciation for your valuable contribution as a Resource Person for the workshop 'ECE to VLSI Chip Design Using Open-Source Tools', held on 19 September 2026, in association with the IETE (ISF) Department of ECE, GCET.”
“Your session provided our students with meaningful technical exposure to VLSI and semiconductor design, and your effort in sharing practical, industry-relevant knowledge added significant value to the workshop.”
“Appreciation to PrimeMOS Research & Solutions for conducting the ECE to VLSI Chip Design Using Open-Source Tools workshop. The session provided students with valuable exposure to VLSI, semiconductor technology, practical learning, and industry-relevant tools. We appreciate the collaboration and look forward to more such technical initiatives.”
“Your commitment to promoting VLSI education, semiconductor technology, practical learning, and technical skill development among students is sincerely appreciated, and your collaboration was instrumental to the success of the workshop.”
Vignan's Bharathi Institute of Technology (VBIT)
"The session was led by PVSDD Mallikarjuna, Founder of PrimeMOS Research and Solutions, who shared valuable insights into VLSI design concepts, industry applications, and emerging trends in semiconductor technology."
"Students gained practical exposure to VLSI fundamentals, design methodologies, and real-world implementation aspects, helping them strengthen their technical foundation and industry readiness."
"An enriching session that bridged academic learning with industry expertise!"
"Gained practical knowledge of LTspice, MOSFET, BJT, and physical design basics. The session clearly demystified how transistor physics translate into actual IC layout and switching performance. Breaking down NMOS and PMOS operation hands-on was extremely beneficial."
A. Karthikeya Reddy 24R11A0404
"Gained practical exposure to LTspice and CMOS basics. From understanding NMOS and PMOS operation to building and simulating NOT and NAND logic gates from scratch, the hands-on approach made semiconductor and chip design concepts crystal clear."
A. Rishi 24R11A0487
"Gained hands-on experience in Cadence schematic design. Navigating industry-grade EDA environments and seeing circuit simulations match theoretical predictions gave me genuine confidence in pursuing VLSI as a core career."
Durga Prasad Reddy
"Gained deep insights into VLSI schematic design, transistor-level simulations, and digital logic synthesis. The session bridged classroom theory directly with real tool execution."
J. V. N. Sastry 24R11A0498
"The practical hands-on with LTspice and open-source EDA software tools helped clarify CMOS inverter behavior and switching delays. Truly inspiring and informative session!"
B. Keerthi 24R11A0405
"Hands-on experience in LTspice creating CMOS NOT gates and analyzing transient characteristics gave us tangible, real-world industry exposure."
L. Naresh 24R11A0420
"The career guidance sessions provided by PrimeMOS helped me understand various opportunities available in the semiconductor and core engineering domains. The discussions were practical, informative, and helpful in planning my future career path."
Ruchitha
"PrimeMOS provided valuable support in project development and IEEE research paper preparation. The guidance on technical documentation, research structure, and implementation approaches helped me improve both my project quality and research understanding."
Mahipal
"The technical workshop and webinar sessions conducted by PrimeMOS offered useful insights into VLSI design concepts, semiconductor technologies, and current industry trends. The sessions were engaging and technically enriching."
Piyush
"I found the workshops and webinars organized by PrimeMOS highly informative. The sessions introduced important semiconductor and VLSI concepts in a structured manner and helped strengthen my technical foundation."
Lalitha
"The career guidance and internship application support provided by PrimeMOS helped me better understand the application process and requirements for research and defense-related internship opportunities. The guidance was professional and encouraging."
Sai Lahari
"The technical workshops and webinars conducted by PrimeMOS provided practical exposure to semiconductor technologies and engineering workflows. The sessions were well organized and beneficial for students interested in core engineering domains."
Gopi
"The VLSI Design workshop conducted by PrimeMOS provided a clear introduction to CMOS and digital design concepts. The explanations were easy to follow and helped me develop greater interest in semiconductor engineering."
Srujana
"The VLSI Design workshop was highly informative and helped me understand the fundamentals of semiconductor design. The session offered valuable exposure to concepts that are not typically covered in detail during regular coursework."
Udaya Lakshmi
"PrimeMOS assisted me in understanding project implementation approaches and converting technical ideas into a structured development plan. The guidance helped me gain confidence in executing my project effectively."
Pravalika
"Presenting my project on a Low-Power 16-bit Vedic Multiplier at the PrimeMOS & TapeoutX event was a fantastic experience. The detailed technical feedback from mentors on my design and timing analysis was extremely helpful in improving my digital design skills."
Bobbala Hema Karthik
"The Semiconductor Ecosystem & VLSI webinar by PrimeMOS and TapeoutX was very informative. It provided a clear picture of the actual steps involved from RTL design to physical verification and fabrication, which is rarely taught in college textbooks."
Naga Varshini Goud Survi
"We presented our SRAM leakage reduction project using Cadence Virtuoso. The expert panel's deep technical questions on transistor sizing and power optimization gave us invaluable insight into professional chip design workflows."
Akhil & Vinisha
"Participating in the project presentation session by PrimeMOS and TapeoutX was very rewarding. The feedback was constructive, pointing out how we could transition our smart attendance system to a more optimized embedded processor architecture."