19 February 2026
VBIT, Hyderabad
Dept. of ECE
The Department of ECE at Vignan's Bharathi Institute of Technology (VBIT) successfully organized a comprehensive Workshop on VLSI Design for III Year ECE students. The session was led by PVSDD Mallikarjuna, Founder of PrimeMOS Research and Solutions, who shared valuable insights into VLSI design concepts, industry applications, and emerging trends in semiconductor technology.
Students gained practical exposure to VLSI fundamentals, CMOS circuit design principles, EDA tools, and RTL-to-GDSII design flow concepts. The event saw enthusiastic participation across both on-campus and online attendees.
150+ Students Participated · Online & Offline
CMOS / VLSI Design
EDA Tools
Semiconductor Trends
RTL-to-GDSII
III Year ECE
19 March 2026
Online · Virtual
PrimeMOS Official
PrimeMOS Research & Solutions successfully conducted an online Technical Webinar and Workshop covering key concepts in Digital Design and VLSI Design, along with hands-on exposure to EDA tools and complete design flow. It was an engaging, knowledge-packed event with active participation from enthusiastic learners across multiple institutes.
Outstanding participants were recognized and awarded digital certificates for their dedication, active involvement, and performance throughout the session.
Best Participant Certificate Winners
Lakshmi Lalitha Ruchitha Vaddi
Piyush Vargish
Jonnakuti Sailahari
Udaya Laxmi Patchapuram
Prathyusha Odugu
Ganeshna
Gopi Krishna Reddy
Mittapalli Praharsha
Digital Design
VLSI Design
EDA Tools
Certificates Awarded
Online
28 June & 1 July 2026
Online · Interactive
PrimeMOS & TapeoutX
PrimeMOS Research & Solutions, in collaboration with TapeoutX, successfully organized a comprehensive webinar on the Semiconductor Ecosystem & VLSI on 28th June, followed by a dedicated student Project Presentation & Q&A session on 1st July. The session brought together close to 90 ECE students and was led by Mr. P V S D D Mallikarjuna (Founder, PrimeMOS), Mr. Lingam Charan (Founder, TapeoutX), and Mr. Lakkimsetty Lakshmi Narasimha Swamy (Co-Founder, TapeoutX).
The sessions covered critical domains like RTL Design, Design Verification, Physical Design, DFT, STA, Fabrication, Embedded Systems, Communication, and Defence Electronics. On 1st July, eight students came back to voluntarily present their own project work, taking peer and mentor feedback.
Student Project Presenters & Topics
Bobbala Hema Karthik — Low-Power 16-bit Vedic Multiplier using Carry Look-Ahead Adder
Nammi Sai Ram — Real-Time Public Transport Tracking System (Offline)
Naga Varshini Goud Survi — NeuroCache
Akhil kumar Chada & Vinisha Veluri — Gated-VDD SRAM Leakage Reduction using Cadence Virtuoso
Gudipudi Nikhita — Smart Attendance Prediction and Alert System
Lokesh Nakka — Muting Phone Automatically in Restricted Zones
Abhilash Kumar Reddy — Smart Helmet
Participant Feedback & Reviews
"Presenting my project on a Low-Power 16-bit Vedic Multiplier at the PrimeMOS & TapeoutX event was a fantastic experience. The detailed technical feedback from mentors on my design and timing analysis was extremely helpful in improving my digital design skills."
- Bobbala Hema Karthik (Student Presenter)
"The session gave me an excellent platform to present my Bus Tracking System. The suggestions from the founders on optimizing the communication interface and microcontroller selection were extremely practical and helped me improve the project."
- Nammi Sai Ram (Student Presenter)
"The Semiconductor Ecosystem & VLSI webinar by PrimeMOS and TapeoutX was very informative. It provided a clear picture of the actual steps involved from RTL design to physical verification and fabrication, which is rarely taught in college textbooks."
- Naga Varshini Goud Survi (Student Participant)
"We presented our SRAM leakage reduction project using Cadence Virtuoso. The expert panel's deep technical questions on transistor sizing and power optimization gave us invaluable insight into professional chip design workflows."
- Akhil Kumar Chada (Student Presenter)
"The collaborative session was a great opportunity to showcase our SRAM layout design. The mentors gave us excellent tips on mitigating leakage currents and optimizing the memory cell layout for fabrication."
- Vinisha Veluri (Student Presenter)
"Participating in the project presentation session by PrimeMOS and TapeoutX was very rewarding. The feedback was constructive, pointing out how we could transition our smart attendance system to a more optimized embedded processor architecture."
- Gudipudi Nikhita (Student Presenter)
"The peer review and mentor feedback during my presentation on restricted-zone phone muting was very helpful. I received great guidance on improving the RF module interface and logic flows."
- Lokesh Nakka (Student Presenter)
"Presenting my Smart Helmet project to industry experts was a major highlight. The advice on sensor integration, power management, and real-time alerts was incredibly valuable for the next phase of development."
- Abhilash Kumar Reddy (Student Presenter)
VLSI Ecosystem
RTL & Physical Design
Project Mentorship
Student Presentations
Career Guidance
24 - 28 August 2026
International · Virtual
PrimeMOS × IEEE SB RRU
PrimeMOS Research & Solutions, in collaboration with IEEE Student Branch RRU, successfully wrapped up its 5-day international workshop on VLSI Design Using Open Source Tools. The event brought together students, faculty, and international participants (including attendees from the Philippines) for a deep dive into the semiconductor ecosystem.
Spanning five interactive days, the workshop covered comprehensive concepts of Open-Source EDA, RTL-to-GDSII workflow, Analog IC flow, CMOS fundamentals, and open-source VLSI design tools, empowering aspiring VLSI engineers with practical industry knowledge.
90+ Voices · Students, Faculty & International Participants
5 Days of Learning
Day 1: Introduction to VLSI & Semiconductor IC Design
Covered VLSI fundamentals, IC design flow, EDA tools, memory & programmable logic.
Day 2: Deep Dive into VLSI Design & Workflows
Covered MOSFET characteristics, CMOS logic gates, first steps into Verilog RTL.
Day 3: Exploring Open-Source EDA Tools
Covered PTL & Transmission Gates, CS/CD amplifiers, building an ALU from scratch.
Day 4: RTL-to-GDSII Implementation (Part 1)
Covered 45nm circuit design, complete RTL-to-GDSII flow, Linux-based EDA workflow.
Day 5: RTL-to-GDSII Conclusion & Feedback
Covered physical design deep-dive, a full counter through synthesis & physical design, complete RTL → Synthesis → Physical Design → GDSII flow.
Highly Rated Participant Feedback (4.5/5)
"This was a very insightful and significant workshop for an aspiring VLSI engineer like me — thank you, PrimeMOS and IEEE SB RRU, for the opportunity! (5/5)"
- Nestor Luis Tappa Jr. (Job Aspirant, Philippines)
"An excellent workshop — Mallikarjuna's coverage of the Analog IC Flow and TCL/Linux was thorough. Would love a follow-up PrimeMOS session on Cadence and TCAD Sentaurus. (5/5)"
- Dr. Mathan N (Faculty)
"Thank you to the IEEE Student Branch RRU and PrimeMOS for organizing this workshop. The sessions were well coordinated and helped me gain practical exposure to open-source VLSI design tools. (5/5)"
- Yamini Sivakumar (B.Tech Student)
"A hands-on implementation of an SoC covering RTL to GDSII in depth would be great for freshers and novices. Thank you for the wonderful experience. (4.5/5)"
- Rohan Manuel Kurian (Industry Professional)
"A very informative and helpful program. I especially enjoyed the theory parts and look forward to practicing the tools touched upon in this course. (4.5/5)"
- Nivedha Gnanodharan (B.Tech Student)
Open-Source EDA
RTL to GDSII
International Workshop
4.5/5 Rating
Hybrid · Online & Offline
Online Webinar
Online Webinar & Presentations
Online Workshop