Partnering with premier universities, professional societies, and semiconductor organizations to equip students with hands-on silicon design exposure.
Active Institutional Proposals: Collaboration proposal under process with Geethanjali College of Engineering & Technology (GCET) for curriculum & ChipIN lab integration; Active collaboration proposal under process with IETE Hyderabad Centre.
2 Proposals Under Process
1 Proposal
IETE
Institution of Electronics & Telecommunication Engineers
Official institutional appreciation and student project outcomes from our hands-on VLSI & EDA tools programs.
Official Letter of Appreciation
6 Oct 2026
4.62 / 5.0 (16 Teams)
“We sincerely appreciate PrimeMOS Research & Solutions for its valuable contribution as Technical Resource Organization for the Two-Day Workshop 'Fundamentals of VLSI: RTL-to-GDSII Flow Using EDA Tools'. The sessions provided students with valuable semiconductor design exposure.”
Andhra Loyola Inst. of Engg. & Tech.
Dept. of ECE & ElectroCratZ Club • ALIET Vijayawada
“Project of 4-bit down counter and got output — Excellent! The complete RTL-to-GDSII flow covering synthesis, floorplanning, CTS, routing, physical verification and GDSII generation was executed with remarkable clarity.”
Challa Niveditha Reddy & Mandagiri Bhavya
B.Tech ECE • ALIET Vijayawada
Project: 4-bit Down Counter (Full Physical Design Flow)
5.0 / 5.0
Team 16 • Perfect Score
“Software implementation of our 4-bit ALU project was excellent. The hands-on training using Linux EDA toolchains, TCL scripting, and understanding real-time digital cell placement made this workshop stand out.”
Balamarthi Ravindra & Snamala Seetaram
B.Tech ECE • ALIET Vijayawada
Project: 4-bit ALU (Arithmetic Logic Unit in Linux/EDA)
A record of our technical outreach — every session built to equip students with real VLSI and semiconductor industry exposure.
Successfully Completed · 16 Student Projects
5th & 6th Oct 2026 ALIET, Vijayawada 16 Teams · 16 Projects Delivered Cadence + Open Source EDA
Two-Day Workshop on Fundamentals of VLSI Design: Complete RTL to GDSII Flow — ALIET
The intensive 2-day workshop “VLSI Design Fundamentals: RTL to GDSII using EDA Tools” was successfully concluded at ALIET in collaboration with ElectroCratZ Technical Club. Led by Mr. P V S D D Mallikarjuna, 16 student teams successfully built and verified 16 complete RTL-to-GDSII digital designs (ALUs, Counters, Sequence Detectors) bridging theory with Cadence & open-source toolchains.
19 Sept 2026 GCET, Hyderabad IETE ISF & ChipIN Proposal Under Process
Workshop on ECE to VLSI Chip Design Using Open Source Tools — GCET
A flagship hands-on workshop organized in collaboration with IETE ISF, Dept. of ECE & ChipIN Centre COE GCET (C2S Programme, MeitY). An official collaboration proposal with GCET is currently under process following the workshop's immense success.
+4
International · Virtual Workshop
24 - 28 Aug 2026 International · Virtual IEEE SB RRU
5-Day International Workshop on VLSI Design Using Open Source Tools
A 5-day international workshop covering the complete RTL-to-GDSII flow using open-source EDA tools, engaging students, faculty, and international participants.
Online Webinar & Presentations
28 June & 1 July 2026 Online · Interactive TapeoutX
Semiconductor & VLSI Career Webinar & Presentations
A dual-session event highlighting the semiconductor ecosystem pathways followed by voluntary student technical project presentations and peer review.
Online Webinar
19 March 2026 Online · Virtual Merit Certificates
Webinar — Digital Design & VLSI with EDA Tools
An engaging online webinar and workshop covering key digital IC design steps, design flows, and hands-on exposure to open-source EDA tools.
Hybrid · Online & Offline
19 Feb 2026 VBIT, Hyderabad Dept. of ECE
Workshop on VLSI Design — VBIT Hyderabad
A comprehensive workshop for III Year ECE students covering VLSI design concepts, CMOS circuit fundamentals, EDA tools, and industry applications.
Visual Showcase & Campus Moments
Event Photo Gallery
Glimpses of hands-on VLSI workshops, laboratory experiments, student project reviews, and academic felicitations with our partners across India.
Felicitation
ALIET Workshop6 Oct 2026
Felicitation & Memento Ceremony
ECE faculty presenting memento honors to Mr. P V S D D Mallikarjuna at the VLSI Design Lab.
Certificates
ALIET Certificates6 Oct 2026
16 Project Teams Honored
Presenting merit and participation certificates to students completing ALU, Counter, and FSM projects.
Technical Lecture
Technical Session5 & 6 Oct 2026
EDA Tools & TCL Scripting Session
Interactive session demonstrating Cadence Xcelium/Genus/Innovus and TCL automation workflows.
Hands-on Lab
VLSI Lab6 Oct 2026
Hands-on RTL to GDSII Lab
Mentoring students through synthesis, placement, routing, DRC/LVS, and layout inspection on laptops.
GCET · 4.8/5
GCET Workshop19 Sept 2026
Official Workshop Poster
Organized by PrimeMOS with IETE ISF GCET and ChipIN Centre COE (C2S Programme).
Felicitation
GCET Lab19 Sept 2026
Felicitation & ChipIN Centre Lab
Memento presentation and group photo with Dr. Appala Raju Uppala sir and students at the C2S ChipIN Lab.
Hands-on Lab
Lab Mentoring19 Sept 2026
Hands-on Lab & Mentoring
Students learning CMOS circuit design, EDA tools, and transistor schematics in real-time.
Certificates
Certificates & Career19 Sept 2026
Career Roadmap & Certificates
Guiding students on industry trajectories and presenting merit/participation certificates.
Collaboration Proposal
IETE AllianceJuly 2026
IETE Hyderabad Strategy Session
Meeting with executive members at IETE Hyderabad Centre on statewide VLSI student outreach.
Leadership
IETE AllianceJuly 2026
IETE Leadership Deliberations
Formal discussions on joint proposals for student semiconductor workshops and design challenges.
150+ Students
Campus Workshop19 Feb 2026
VBIT Hyderabad Workshop
Hands-on VLSI fundamentals, CMOS design principles, and EDA design flows for 150+ engineers.
International
International Workshop24-28 Aug 2026
5-Day Open-Source VLSI Workshop
Comprehensive 5-day hands-on program with IEEE Student Branch RRU engaging global participants.
Merit Awards
Online Webinar19 Mar 2026
Digital Design & VLSI Webinar
Interactive session on EDA workflows followed by best participant digital certificate awards.
8 Projects
Industry Partner28 Jun & 1 Jul 2026
TapeoutX Student Project Forum
Joint industry session with TapeoutX founders featuring 8 student design presentations.
For Colleges & Institutions
Organise a Workshop or Webinar at Your College
Bring PrimeMOS™ to your campus! We deliver highly engaging, syllabus-complementary technical sessions on VLSI, CMOS Design, EDA Tools, Digital Design, and Semiconductor Fabrication Concepts — tailored specifically to your students' academic level and curriculum.
Custom-designed workshop modules aligned to your department's academic needs
Conducted by an IEEE-published VLSI researcher with industry mentorship experience
Available in both online (webinar) and offline (on-campus) formats
Certificates of participation issued to all attendees
Proven track record — 150+ students engaged across VBIT Hyderabad and online sessions
Flexible scheduling — weekday or weekend, theory or lab-integrated sessions
Pricing for college events is discussed on a case-by-case basis. Contact us to get a custom quote for your institution.
Book a Session
Reach out via any of the channels below with your college name, department, approximate student count, and preferred dates. We'll get back to you promptly.
5th & 6th October 2026 Andhra Loyola Inst. of Engg. & Tech. (ALIET), Vijayawada ElectroCratZ • ECE Technical Club Successfully Completed
RTL to GDSII Workshop Successfully Completed
The “VLSI Design Fundamentals: RTL to GDSII using EDA Tools” workshop concluded with resounding success on 5th & 6th October 2026. Hosted in collaboration with ElectroCratZ (Dept. of ECE, ALIET - Autonomous) and presented by Mr. P V S D D Mallikarjuna (Founder, PrimeMOS), students bridged academic digital concepts with real semiconductor industry workflows.
Day 1: Build the Environment → Day 2: Build the Design → RTL to GDSII
16
Student Teams
16
RTL to GDSII Projects
5
Live Demo Projects
Cadence + OpenEDA
Industry Toolchains
Industry EDA Toolchains & Environment
Cadence Xcelium Cadence Genus Cadence Innovus Yosys Synthesis OpenROAD P&R GTKWave WSL Setup Ubuntu Linux TCL Scripting Verilog HDL
Workshop Day-wise Roadmap & Highlights
VLSI Fundamentals & MOSFET Physics
Explored MOSFET operation principles, NMOS & PMOS switching behavior, evolution of Integrated Circuits (ICs), and understanding core PPA (Power, Performance & Area) design tradeoffs in modern silicon.
Commercial Cadence EDA Demonstration
Live industrial demonstration covering Cadence Xcelium (digital simulation), Cadence Genus (RTL logic synthesis), and Cadence Innovus (Place & Route physical layout).
Environment Setup: WSL, Ubuntu & Open EDA
Configured students' laptops with WSL (Windows Subsystem for Linux), Ubuntu Linux environment, compilers, and complete open-source EDA toolchains preparing them for hands-on automation.
TCL Scripting & Flow Automation
Mastered TCL scripting fundamentals tailored for RTL design flows, timing constraints, synthesis scripting, and hands-on automation across open EDA toolchains.
5 Live Demonstration Projects
Interactive real-time demonstrations taking complete digital blocks through simulation, logic synthesis, floorplanning, placement, CTS, routing, and GDSII generation.
16 Student Teams — 16 RTL to GDSII Projects
Students formed 16 project teams, independently coding Verilog RTL, validating waveforms, performing synthesis, and generating physical GDSII streams for custom digital architectures.
VLSI Domain Career Roadmap
Detailed career guidance spanning RTL Design, Functional Verification, Physical Design (PD), Analog Mixed-Signal, DFT, and EDA tooling pathways in the semiconductor sector.
Student Hands-on Projects (16 Teams • 16 Completed)
Filter and inspect the designs taken through the physical design flow by student teams:
8-Bit Configurable ALU
Teams 1 & 2 • Arithmetic & Logic • RTL → GDSII
4-Bit Fast Adder-Subtractor
Teams 3 & 4 • CLA Logic • RTL → GDSII
Synchronous Up/Down Counter
Teams 5 & 6 • Modulo-16 • RTL → GDSII
BCD Decade & Ring Counters
Teams 7 & 8 • Timing Logic • RTL → GDSII
1011 Sequence Detector (Mealy)
Teams 9 & 10 • Overlapping FSM • RTL → GDSII
1101 Pattern Detector (Moore)
Teams 11 & 12 • Non-Overlapping • RTL → GDSII
Traffic Light State Controller
Teams 13 & 14 • FSM Controller • RTL → GDSII
Priority Encoder & Shifters
Teams 15 & 16 • Barrel Shifter • RTL → GDSII
Interactive RTL to GDSII Flow
Click each stage to inspect the tools and processes executed during the workshop:
1. RTL Design & Modeling: Writing synthesizable Verilog HDL descriptions for ALUs, counters, and FSM sequence detectors.
2. Functional Simulation: Testbench stimulus generation, functional waveform verification using Cadence Xcelium and GTKWave.
3. Logic Synthesis: Translating RTL to gate-level netlists mapped to standard cell libraries using Cadence Genus and Yosys.
4. Floorplanning & PPA: Die sizing, core aspect ratio, power distribution grid (PDN), and I/O pad placement with PPA optimization.
5. Placement & CTS: Standard cell legalization, Clock Tree Synthesis (CTS) for minimal clock skew, latency, and setup/hold timing closure.
6. Detailed Routing: Global and detail metal routing interconnecting gates and clock trees with zero design rule violations using Cadence Innovus & OpenROAD.
7. Physical Verification: Running automated Design Rule Checks (DRC) and Layout Versus Schematic (LVS) cleanly matching netlist.
8. GDSII Stream Tapeout: Final manufacturing binary layout stream generation ready for semiconductor foundry fabrication.
19 September 2026 VLSI Design Lab, GCET Hyderabad IETE ISF & ChipIN Centre 4.8 / 5.0 Feedback Rating
PrimeMOS Research & Solutions™ successfully conducted an intensive, highly rated hands-on workshop on "ECE to VLSI Chip Design Using Open-Source Tools" at Geethanjali College of Engineering and Technology (GCET), Keesara. The full-day session was led by Mr. P V S D D Mallikarjuna, Founder of PrimeMOS Research & Solutions™, serving as Resource Person.
The workshop was organized in close collaboration with the IETE ISF GCET, the Analog and Digital Electronics Group (Dept. of ECE, GCET), and the ChipIN Centre COE GCET under the national Chips to Start-up (C2S) Programme (supported by C-DAC Bangalore, an initiative of MeitY, Govt. of India).
Exceptional Impact: Seeing students go from "what is a MOSFET" to placing and routing their own designs in a single day — validated by a remarkable 4.8/5 feedback score!
Official Collaboration Proposal Under Process
Following the resounding success of the 19th September hands-on workshop, an official collaboration proposal between PrimeMOS Research & Solutions™ and Geethanjali College of Engineering and Technology (GCET) is currently under active process to establish sustained VLSI design training, laboratory integration, faculty enablement, and joint semiconductor design exploration with GCET's ChipIN Centre (C2S Programme, MeitY).
Chips to Start-up (C2S) Infrastructure: Utilizing GCET's ChipIN Centre resources, server architectures, and EDA licenses.
Career Roadmaps (2026–2035): Skill matrices mapped to VLSI jobs across RTL design, Physical Design, Verification, and DFT.
Hands-on CMOS Practicals: Practical design and simulation using Cadence Virtuoso and LTspice.
Feedback & Testimonials
4.8 / 5.0 Feedback Rating
Geethanjali College of Engineering & Technology, Keesara
“Appreciation to PrimeMOS Research & Solutions for conducting the ECE to VLSI Chip Design Using Open-Source Tools workshop. The session provided students with valuable exposure to VLSI, semiconductor technology, practical learning, and industry-relevant tools. We appreciate the collaboration and look forward to more such technical initiatives.”
— Dept. of Electronics & Communication Engineering & IETE (ISF) GCET
A. Karthikeya Reddy 5/5
B.Tech ECE (24R11A0404)
“Gained practical knowledge of LTspice, MOSFET, BJT, and physical design basics.”
A. Rishi 5/5
B.Tech ECE (24R11A0487)
“Gained practical exposure to LTspice and CMOS basics.”
Durga Prasad Reddy 5/5
B.Tech ECE • GCET
“Gained hands-on experience in Cadence schematic design.”
• Dr. Appala Raju Uppala sir — Sincere gratitude for wonderful hospitality, faculty support, and for making the whole day run smoothly.
• Dr. G. Sreelakshmi mam (HoD-ECE) & the ChipIN Centre (C2S Programme) Team — For leadership and providing access to industry-grade Cadence EDA tools that enabled impactful hands-on sessions.
• Bhavani Bhanu & Coordinators of IETE_ISF GCET — For exceptional student coordination, lab logistics, and smooth session execution.
Proposal Under ProcessCadence InnovusCadence VirtuosoOpen-Source EDAChipIN Centre (C2S)IETE ISF GCET4.8/5 Rating
The Department of ECE at Vignan's Bharathi Institute of Technology (VBIT) successfully organized a comprehensive Workshop on VLSI Design for III Year ECE students. The session was led by PVSDD Mallikarjuna, Founder of PrimeMOS Research and Solutions, who shared valuable insights into VLSI design concepts, industry applications, and emerging trends in semiconductor technology.
Students gained practical exposure to VLSI fundamentals, CMOS circuit design principles, EDA tools, and RTL-to-GDSII design flow concepts. The event saw enthusiastic participation across both on-campus and online attendees.
150+ Students Participated · Online & Offline
CMOS / VLSI DesignEDA ToolsSemiconductor TrendsRTL-to-GDSIIIII Year ECE
PrimeMOS Research & Solutions successfully conducted an online Technical Webinar and Workshop covering key concepts in Digital Design and VLSI Design, along with hands-on exposure to EDA tools and complete design flow. It was an engaging, knowledge-packed event with active participation from enthusiastic learners across multiple institutes.
Outstanding participants were recognized and awarded digital certificates for their dedication, active involvement, and performance throughout the session.
28 June & 1 July 2026 Online · Interactive PrimeMOS & TapeoutX
PrimeMOS Research & Solutions, in collaboration with TapeoutX, successfully organized a comprehensive webinar on the Semiconductor Ecosystem & VLSI on 28th June, followed by a dedicated student Project Presentation & Q&A session on 1st July. The session brought together close to 90 ECE students and was led by Mr. P V S D D Mallikarjuna (Founder, PrimeMOS), Mr. Lingam Charan (Founder, TapeoutX), and Mr. Lakkimsetty Lakshmi Narasimha Swamy (Co-Founder, TapeoutX).
The sessions covered critical domains like RTL Design, Design Verification, Physical Design, DFT, STA, Fabrication, Embedded Systems, Communication, and Defence Electronics. On 1st July, eight students came back to voluntarily present their own project work, taking peer and mentor feedback.
Student Project Presenters & Topics
Bobbala Hema Karthik — Low-Power 16-bit Vedic Multiplier using Carry Look-Ahead Adder
Nammi Sai Ram — Real-Time Public Transport Tracking System (Offline)
Gudipudi Nikhita — Smart Attendance Prediction and Alert System
Lokesh Nakka — Muting Phone Automatically in Restricted Zones
Abhilash Kumar Reddy — Smart Helmet
Participant Feedback & Reviews
"Presenting my project on a Low-Power 16-bit Vedic Multiplier at the PrimeMOS & TapeoutX event was a fantastic experience. The detailed technical feedback from mentors on my design and timing analysis was extremely helpful in improving my digital design skills."
- Bobbala Hema Karthik (Student Presenter)
"The session gave me an excellent platform to present my Bus Tracking System. The suggestions from the founders on optimizing the communication interface and microcontroller selection were extremely practical and helped me improve the project."
- Nammi Sai Ram (Student Presenter)
"The Semiconductor Ecosystem & VLSI webinar by PrimeMOS and TapeoutX was very informative. It provided a clear picture of the actual steps involved from RTL design to physical verification and fabrication, which is rarely taught in college textbooks."
- Naga Varshini Goud Survi (Student Participant)
"We presented our SRAM leakage reduction project using Cadence Virtuoso. The expert panel's deep technical questions on transistor sizing and power optimization gave us invaluable insight into professional chip design workflows."
- Akhil Kumar Chada (Student Presenter)
"The collaborative session was a great opportunity to showcase our SRAM layout design. The mentors gave us excellent tips on mitigating leakage currents and optimizing the memory cell layout for fabrication."
- Vinisha Veluri (Student Presenter)
"Participating in the project presentation session by PrimeMOS and TapeoutX was very rewarding. The feedback was constructive, pointing out how we could transition our smart attendance system to a more optimized embedded processor architecture."
- Gudipudi Nikhita (Student Presenter)
"The peer review and mentor feedback during my presentation on restricted-zone phone muting was very helpful. I received great guidance on improving the RF module interface and logic flows."
- Lokesh Nakka (Student Presenter)
"Presenting my Smart Helmet project to industry experts was a major highlight. The advice on sensor integration, power management, and real-time alerts was incredibly valuable for the next phase of development."
24 - 28 August 2026 International · Virtual PrimeMOS × IEEE SB RRU
PrimeMOS Research & Solutions, in collaboration with IEEE Student Branch RRU, successfully wrapped up its 5-day international workshop on VLSI Design Using Open Source Tools. The event brought together students, faculty, and international participants (including attendees from the Philippines) for a deep dive into the semiconductor ecosystem.
Spanning five interactive days, the workshop covered comprehensive concepts of Open-Source EDA, RTL-to-GDSII workflow, Analog IC flow, CMOS fundamentals, and open-source VLSI design tools, empowering aspiring VLSI engineers with practical industry knowledge.
90+ Voices · Students, Faculty & International Participants
"This was a very insightful and significant workshop for an aspiring VLSI engineer like me — thank you, PrimeMOS and IEEE SB RRU, for the opportunity! (5/5)"
- Nestor Luis Tappa Jr. (Job Aspirant, Philippines)
"An excellent workshop — Mallikarjuna's coverage of the Analog IC Flow and TCL/Linux was thorough. Would love a follow-up PrimeMOS session on Cadence and TCAD Sentaurus. (5/5)"
- Dr. Mathan N (Faculty)
"Thank you to the IEEE Student Branch RRU and PrimeMOS for organizing this workshop. The sessions were well coordinated and helped me gain practical exposure to open-source VLSI design tools. (5/5)"
- Yamini Sivakumar (B.Tech Student)
"A hands-on implementation of an SoC covering RTL to GDSII in depth would be great for freshers and novices. Thank you for the wonderful experience. (4.5/5)"
- Rohan Manuel Kurian (Industry Professional)
"A very informative and helpful program. I especially enjoyed the theory parts and look forward to practicing the tools touched upon in this course. (4.5/5)"
- Nivedha Gnanodharan (B.Tech Student)
Open-Source EDARTL to GDSIIInternational Workshop4.5/5 Rating
Successfully Completed · 16 Student Projects
Completed Event · 4.8/5 Rating
International · Virtual Workshop
Online Webinar & Presentations
Online Webinar
Hybrid · Online & Offline
